Field effect transistors (FETS) are common devices of integrated circuitry. One method of tailoring the properties of an FET is to adjust the dopant level within a channel region device, which can adjust a threshold voltage of the device. Dopants provided within the channel regions of FETs are frequently referred to as threshold voltage implants, due to the effect that such dopants can have on threshold voltage.
FIG. 1 shows a construction 10 comprising an exemplary prior art FET 12. The FET is supported by a semiconductor substrate 14. Substrate 14 can comprise any suitable semiconductor material, and in particular aspects can comprise, consist essentially of or consist of monocrystalline silicon lightly background-doped with p-type dopant. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Substrate 14 can be part of a monocrystalline silicon wafer, and accordingly can correspond to so-called bulk silicon. In other aspects of the prior art, substrate 14 can correspond to a thin layer of semiconductive material which is formed over a layer of insulative material (not shown), and accordingly can be part of a silicon-on-insulator (SOI) construction.
Transistor device 12 comprises a pair of source/drain regions 16 and 18 extending within the semiconductor substrate 14. Source/drain regions 16 and 18 correspond to conductively-doped diffusion regions, and can comprise one or both of n-type dopant and p-type dopant.
Transistor device 12 also includes electrically conductive gateline material 20 over substrate 14 and between the regions 16 and 18. Gateline material 20 forms a gate 13 of the transistor device, and can comprise any suitable conductive material or combination of conductive materials. In particular aspects, gateline material 20 can comprise one or more electrically conductive materials selected from the group consisting of metals, metal compounds, and conductively-doped silicon. Gateline material 20 can be a portion of a wordline which extends in a direction orthogonal to the surface of the page of FIG. 1.
Although the gateline material 20 is shown to comprise electrically conductive material throughout the entire thickness, it is to be understood that the gateline material 20 would typically be capped by an electrically insulative material, such as, for example, a material comprising one or both of silicon dioxide and silicon nitride (not shown).
A pair of electrically insulative sidewall spacers 22 and 24 extend along opposing sidewalls of gate 13. Spacers 22 and 24 can comprise any suitable electrically insulative material, and in particular aspects can comprise one or both of silicon dioxide and silicon nitride.
Gateline material 20 is separated from semiconductor material 14 by a dielectric material 26. Dielectric material 26 can comprise any suitable material or combination of materials, and in particular aspects will comprise, consist essentially of, or consist of silicon dioxide.
Transistor device 12 comprises a channel region 28 beneath the gate 13, and between source/drain regions 16 and 18. In operation, gate 13 is utilized to turn on electrical flow within the channel region 28, and to thereby electrically connect source/drain regions 16 and 18 with one another. The voltage at which the gate turns on electrical flow between source/drain regions 16 and 18 is referred to as a threshold voltage, and the magnitude of such threshold voltage can be influenced by the amount and type of dopant present within channel region 28.
A continuing goal during semiconductor device fabrication is to reduce the number of process steps. Accordingly, processing steps associated with fabrication of separate devices are combined. Generally, there will be numerous FETs formed simultaneously, and some of the FETs will be fabricated differently than others during threshold voltage implanting so that the threshold voltage implants of particular devices can be tailored for specific applications of the devices. An exemplary prior art method of forming prior art FETs having different threshold voltage implants relative to one another is described with reference to FIGS. 2-5.
Referring initially to FIG. 2, a semiconductor construction 50 is illustrated at a preliminary processing stage. Construction 50 comprises the substrate 14, gate dielectric 26, and gateline material 20 described previously with respect to FIG. 1. The gateline material 20 and dielectric material 26 are not yet patterned into the gate shape at the processing stage of FIG. 2.
Construction 50 is divided amongst a first segment 52 over which a first transistor device will be formed and a second segment 54 over which a second transistor device will be formed. The first and second transistor devices will have different threshold voltage implants relative to one another. It is to be understood that the first transistor device will typically be part of a set of first devices fabricated identically relative to one another, and a second transistor device will typically be part of a set of second transistor devices which are also fabricated identically to one another.
A masking material 56 is provided over the first segment 52, and not over the second segment 54. Subsequently, a threshold voltage implant is conducted to implant dopant 60 into substrate 14. The masking material 56 prevents dopant 60 from penetrating into the substrate 14 associated with segment 52, while the unprotected segment 54 has dopant 60 penetrating therein to form a threshold voltage implant region 62 within substrate 14 (the threshold voltage implant region is demarcated with a dashed line in FIG. 2). The masking material 56 utilized to protect segment 52 can comprise any suitable material, and in particular aspects will comprise, consist essentially of or consist of photoresist. In such aspects, masking material 56 can be patterned into a desired shape utilizing photolithographic processing.
Referring next to FIG. 3, masking material 56 (FIG. 2) is stripped from over construction 50, and another masking material 63 is formed to be over segment 54 and not over segment 52. Subsequently, a dopant 64 is implanted into segment 52 to form a threshold voltage implant 66. Masking material 63 prevents dopant 64 from entering the substrate 14 of segment 54. Masking material 63 can comprise the same compositions discussed above regarding masking material 56, and accordingly, can, in particular aspects, comprise, consist essentially of or consist of photoresist.
Referring next to FIG. 4, masking material 63 (FIG. 3) is removed. Since the threshold voltage implant regions 62 and 66 are formed at different times relative one another, the implant regions can be formed to comprise different dopant concentrations relative to one another. Accordingly, the regions 62 and 66 can be specifically tailored for different transistor device applications relative to one another.
Referring next to FIG. 5, transistor constructions 70 and 72 are formed over segments 52 and 54, respectively. Transistor construction 70 comprises source/drain regions 74 and 76, a gate 78 patterned from gateline material 20 and dielectric material 26, and sidewall spacers 80 formed along sidewalls of gate 78. Transistor device 72 comprises source/drain regions 82 and 84, a gate 86 patterned from gateline material 20 and dielectric material 26, and sidewall spacers 88 formed along sidewalls of gate 86.
The channel implant regions 62 and 66 form channel regions for gates 72 and 70, respectively. Since the channel implant regions were formed at different times relative to one another and can comprise different dopant concentrations (and in some aspects different dopant types) relative to one another, the threshold voltage of transistor device 72 can be tailored to be different than that of device 70 through the type of implant utilized for region 62 relative to that utilized for region 66.
It is desired to develop new methods for forming multiple transistors which are improved relative to the methods discussed above in one or both of the number of processing steps utilized and the complexity of the processing steps utilized.
Although the invention was motivated, at least in part, by the desire to develop new methodologies for simultaneously forming differently tailored threshold voltage implants amongst a plurality of transistor devices, the invention is not limited to such applications.